Each DMA channel has a 16-bit address register and a 16-bit count register associated with it.
2.
A PIT may either count down from some value to zero, or up to the capacity of the count register, overflowing to zero.
3.
The channel 0 Current Address register is the source for the data transfer and channel 1 and the transfer terminates when Current Word Count register becomes 0.
4.
To initiate a data transfer the device driver sets up the DMA channel's address and count registers together with the direction of the data transfer, read or write.
5.
Standard US medical practice has been that men whose PSA counts register lower than 4, and whose rectal exams suggest nothing amiss, do not need to have a biopsy to check for cancer.
6.
The " data break " method moved some of common logic needed to implement DMA I / O from each I / O device into one common copy of the logic within the processor . " Data break " placed the processor in charge of maintaining the DMA address and word count registers.
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